41 lines
1.2 KiB
Coq
41 lines
1.2 KiB
Coq
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`timescale 1ns / 1ps
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module ZX8401 (
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input wire drasll,
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input wire mreqdl,
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input wire mreq,
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input wire [13:0] a,
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input wire a15,
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input wire ts1,
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input wire ts2,
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input wire rd,
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input wire wr,
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output wire [7:0] ma,
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output wire [6:0] dma,
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output wire casl
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);
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wire rd_wr = !(rd & wr);
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wire rd_wr_a15 = !(rd_wr & a15);
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wire avb = mreqdl | rd_wr_a15;
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assign dma[5] = (drasll & a[5]) | (!drasll & a[12]);
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assign dma[4] = (drasll & a[4]) | (!drasll & a[11]);
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assign dma[3] = (drasll & a[3]) | (!drasll & a[10]);
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assign dma[6] = (drasll & a[6]) | (!drasll & a[13]);
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assign ma[5] = (avb & a[5]) | (!avb & a[12]);
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assign ma[4] = (avb & a[4]) | (!avb & a[11]);
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assign ma[3] = (avb & a[3]) | (!avb & a[10]);
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assign ma[6] = (avb & a[6]) | (!avb & a[13]);
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assign dma[4] = (drasll & a[1]) | (!drasll & a[8]);
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assign dma[0] = (drasll & a[0]) | (!drasll & a[7]);
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assign dma[1] = (drasll & a[8]) | (!drasll & a[1]);
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assign dma[2] = (drasll & a[2]) | (!drasll & a[9]);
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assign ma[2] = (avb & a[1]) | (!avb & a[8]);
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assign ma[0] = (avb & a[0]) | (!avb & a[7]);
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assign ma[7] = (avb & ts2) | (!avb & ts1);
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assign ma[1] = (avb & a[2]) | (!avb & a[9]);
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assign casl = mreq | avb;
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endmodule
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