`timescale 1ns / 1ps

module ZX8401 (
    input wire  drasll,
    input wire  mreqdl,
    input wire  mreq,
    input wire  [13:0] a,
    input wire  a15,
    input wire  ts1,
    input wire  ts2,
    input wire  rd,
    input wire  wr,
    output wire [7:0] ma,
    output wire [6:0] dma,
    output wire casl
);

wire rd_wr     = !(rd & wr);
wire rd_wr_a15 = !(rd_wr & a15);
wire avb       = mreqdl | rd_wr_a15;

assign dma[5] = (drasll & a[5]) | (!drasll & a[12]);
assign dma[4] = (drasll & a[4]) | (!drasll & a[11]);
assign dma[3] = (drasll & a[3]) | (!drasll & a[10]);
assign dma[6] = (drasll & a[6]) | (!drasll & a[13]);
assign ma[5]  = (avb & a[5])    | (!avb & a[12]);
assign ma[4]  = (avb & a[4])    | (!avb & a[11]);
assign ma[3]  = (avb & a[3])    | (!avb & a[10]);
assign ma[6]  = (avb & a[6])    | (!avb & a[13]);
assign dma[4] = (drasll & a[1]) | (!drasll & a[8]);
assign dma[0] = (drasll & a[0]) | (!drasll & a[7]);
assign dma[1] = (drasll & a[8]) | (!drasll & a[1]);
assign dma[2] = (drasll & a[2]) | (!drasll & a[9]);
assign ma[2]  = (avb & a[1])    | (!avb & a[8]);
assign ma[0]  = (avb & a[0])    | (!avb & a[7]);
assign ma[7]  = (avb & ts2)     | (!avb & ts1);
assign ma[1]  = (avb & a[2])    | (!avb & a[9]);
assign casl   = mreq | avb;

endmodule