xan/tabby
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Actually bother to stop and restart SPI timer when needed

Browse source
This commit is contained in:
XANTRONIX Development 2016-06-02 00:01:50 -05:00
parent 8e460b56ea
commit 5762889c5a
1 changed files with 51 additions and 47 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

98
avr/send.c
View file

@ -7,7 +7,6 @@
#include <tabby/avr/uart.h> #include <tabby/avr/uart.h>
#define TIMER0_INTERVAL 1953 #define TIMER0_INTERVAL 1953
#define PACKET_BODY_SIZE 640
enum { enum {
TABBY_SEND_READING = 0, TABBY_SEND_READING = 0,
@ -25,7 +24,7 @@ static volatile tabby_printer_packet header = {
.size = 0 .size = 0
}; };
static volatile uint8_t body[PACKET_BODY_SIZE]; static volatile uint8_t body[TABBY_PRINTER_MAX_PACKET_SIZE];
static volatile uint16_t sum = 0x0000; static volatile uint16_t sum = 0x0000;
@ -36,14 +35,52 @@ static volatile uint8_t device = 0x00,
static volatile uint16_t i = 0, static volatile uint16_t i = 0,
b = 0; b = 0;
/* static void spi_start() {
* Internal clock source interrupt vector /*
*/ * Configure MISO as output
ISR(TIMER0_COMPB_vect) { */
if (!(flags & TABBY_SEND_BUFFERED)) { DDRB |= (1 << DDB4);
reti();
}
/*
* Configure MOSI as input
*/
DDRB &= ~(1 << DDB3);
/*
* Configure SCK pin as output
*/
DDRB |= (1 << DDB5);
/*
* Enable timer interrupt vector
*/
TIMSK0 = (1 << TOIE1);
/*
* Reset timer counter to zero
*/
TCNT1 = 0;
/*
* Set timer interval
*/
OCR1A = TIMER0_INTERVAL;
/*
* Set timer clock divider to 1/1
*/
TCCR1B = (1 << CS10);
}
static void spi_end() {
DDRB &= ~((1 << DDB5) | (1 << DDB4) | (1 << DDB3));
TIMSK0 &= ~(1 << TOIE1);
TCNT1 = 0;
OCR1A = TIMER0_INTERVAL;
TCCR1B = (1 << CS10);
}
ISR(TIMER0_COMPB_vect) {
value_in >>= 1; value_in >>= 1;
PORTB |= (1 << PORTB5); PORTB |= (1 << PORTB5);
@ -83,6 +120,8 @@ ISR(TIMER0_COMPB_vect) {
b = 0; b = 0;
flags &= ~TABBY_SEND_BUFFERED; flags &= ~TABBY_SEND_BUFFERED;
flags |= TABBY_SEND_COMPLETE; flags |= TABBY_SEND_COMPLETE;
spi_end();
} }
bits = 8; bits = 8;
@ -97,43 +136,6 @@ ISR(TIMER0_COMPB_vect) {
PORTB &= ~(1 << PORTB5); PORTB &= ~(1 << PORTB5);
} }
static void clock_setup() {
/*
* Configure MISO as output
*/
DDRB |= (1 << DDB4);
/*
* Configure MOSI as input
*/
DDRB &= ~(1 << DDB3);
/*
* Configure SCK pin as output
*/
DDRB |= (1 << DDB5);
/*
* Enable timer interrupt vector
*/
TIMSK0 = (1 << TOIE1);
/*
* Reset timer counter to zero
*/
TCNT1 = 0;
/*
* Set timer interval
*/
OCR1A = TIMER0_INTERVAL;
/*
* Set timer clock divider to 1/1
*/
TCCR1B = (1 << CS10);
}
static uint16_t checksum() { static uint16_t checksum() {
uint16_t sum = 0; uint16_t sum = 0;
size_t i; size_t i;
@ -154,7 +156,7 @@ int main() {
uart_init(); uart_init();
clock_setup(); spi_start();
sei(); sei();
@ -237,6 +239,8 @@ int main() {
i = 0; i = 0;
b = 0; b = 0;
flags |= TABBY_SEND_BUFFERED; flags |= TABBY_SEND_BUFFERED;
spi_start();
} }
} }
} }